1. Field of the Invention
The present invention relates to a static random access memory (SRAM) cell having thin film transistors.
2. Description of the Related Art
Generally, an SRAM cell is constructed by a flip-flop formed by cross-coupled inverters, and transfer gates between the nodes of the flip-flop and bit lines.
Also, in a prior art SRAM cell, in order to reduce the cell size, each of the inverters is constructed by a load P-channel thin film transistor (TFT) and a drive N-channel MOS (bulk) drive transistor. In this case, the bit lines form parasitic thin film transistors with source-channel-drain layers of the load thin film transistors. This will be explained later in detail.
In the above-described prior art SRAM cell, however, the parasitic thin film transistors are operated so as to impede the operation of the load thin film transistors. As a result, it is difficult to operate the SRAM cell at a lower voltage, and also, the stability of the SRAM cell is reduced.